Double Data Rate DDR) SDRAM is the other competing memory technology battling to provide system builders with a high-performance alternative to Direct RDRAM. As in standard SDRAM, DDR SDRAM is tied to the system’s FSB, the memory and bus executing instructions at the same time rather than one of them having to wait for the other.
Traditionally, to synchronise logic devices, data transfers would occur on a clock edge. As a clock pulse oscillates between 1 and 0, data would be output on either the rising edge (as the pulse changes from a 0 to a 1) or on the falling edge. DDR DRAM works by allowing the activation of output operations on the chip to occur on both the rising and falling edge of the clock, thereby providing an effective doubling of the clock frequency without increasing the actual frequency.
DDR-DRAM first broke into the mainstream PC arena in late 1999, when it emerged as the memory technology of choice on graphics cards using nVidia’s GeForce 256 3D graphics chip. Lack of support from Intel delayed its acceptance as a main memory technology. Indeed, when it did begin to be used as PC main memory, it was no thanks to Intel. This was late in 2000 when AMD rounded off what had been an excellent year for the company by introducing DDR-DRAM to the Socket A motherboard. While Intel appeared happy for the Pentium III to remain stuck in the world of PC133 SDRAM and expensive RDRAM, rival chipset maker VIA wasn’t, coming to the rescue with the DDR-DRAM supporting Pro266 chipset.
By early 2001, DDR-DRAM’s prospects had taken a major turn for the better, with Intel at last being forced to contradict its long-standing and avowed backing for RDRAM by announcing a chipset – codenamed Brookdale – that would be the company’s first to support the DDR-DRAM memory technology. The i845 chipset duly arrived in mid-2001, although it was not before the beginning of 2002 that system builders would be allowed to couple it with DDR SDRAM.
DDR memory chips are commonly referred to by their data transfer rate. This value is calculated by doubling the bus speed to reflect the double data rate. For example, a DDR266 chip sends and receives data twice per clock cycle on a 133MHz memory bus. This results in a data transfer rate of 266MT/s (million transfers per second). Typically, 200MT/s (100MHz bus) DDR memory chips are called DDR200, 266MT/s (133MHz bus) chips are called DDR266, 333MT/s (166MHz bus) chips are called DDR333 chips, and 400MT/s (200MHz bus) chips are called DDR400.
DDR memory modules, on the other hand, are named after their peak bandwidth – the maximum amount of data they can deliver per second – rather than their clock rates. This is calculated by multiplying the amount of data a module can send at once (called the data path) by the speed the FSB is able to send it. The data path is measured in bits, and the FSB in MHz.
A PC1600 memory module (simply the DDR version of PC100 SDRAM) uses DDR200 chips and can deliver bandwidth of 1600MBps. PC2100 (the DDR version of PC133 SDRAM) uses DDR266 memory chips, resulting in 2100MBps of bandwidth. PC2700 modules use DDR333 chips to deliver 2700MBps of bandwidth and PC3200 – the fastest widely used form in late 2003 – uses DDR400 chips to deliver 3200MBps of bandwidth.
DDR400 was to prove the limit of DDR technology. In the spring of 2004, the next step in the evolutionary chain emerged, in the shape of the the new DDR2 memory architecture.
- What is Level 1 (L1) Cache Memory?
- What is L2 (Level 2) cache memory?
- RAM or Main Memory – PC / computer memory (DIMM, DRAM, SDRAM)
- DRAM – Dynamic Random Access Memory
- FPM DRAM
- EDO (Extended Data Out) and BEDO (Burst Extended Data Out) DRAM
- PC133 SDRAM
- DDR SDRAM explained
- DDR2 DRAM
- Dual Channel DDR Memory
- 1T SRAM
- Direct DRAM
- DIMM Memory
- RIMMs Memory
- Memory Presence Detection
- Parity Memory
- ECC Memory
- Memory Upgrades
- The Evolution of Memory
- Flash Memory
- Magnetic RAM
Wrong. 266 MT/s means the clock is triggered at 133 MHz but the memory data bus does work physically at 266 MHz. Your “(bus 133 MHz)” is simply technically wrong.