What is L2 (Level 2) cache memory?

Most PCs are offered with a Level 2 cache to bridge the processor/memory performance gap. Level 2 cache – also referred to as secondary cache) uses the same control logic as Level 1 cache and is also implemented in SRAM.

Level 2 cache typically comes in two sizes, 256KB or 512KB, and can be found, or soldered onto the motherboard, in a Card Edge Low Profile (CELP) socket or, more recently, on a COAST (“cache on a stick”) module. The latter resembles a SIMM but is a little shorter and plugs into a COAST socket, which is normally located close to the processor and resembles a PCI expansion slot. The Pentium Pro deviated from this arrangement, siting the Level 2 cache on the processor chip itself.

The aim of the Level 2 cache is to supply stored information to the processor without any delay (wait-state). For this purpose, the bus interface of the processor has a special transfer protocol called burst mode. A burst cycle consists of four data transfers where only the address of the first 64 are output on the address bus. The most common Level 2 cache is synchronous pipeline burst.

To have a synchronous cache a chipset, such as Triton, is required to support it. It can provide a 3-5% increase in PC performance because it is timed to a clock cycle. This is achieved by use of specialised SRAM technology which has been developed to allow zero wait-state access for consecutive burst read cycles. Pipelined Burst Static RAM (PB SRAM) has an access time in the range 4.5 to 8 nanoseconds (ns) and allows a transfer timing of 3-1-1-1 for bus speeds up to 133MHz. These numbers refer to the number of clock cycles for each access of a burst mode memory read. For example, 3-1-1-1 refers to three clock cycles for the first word and one cycle for each subsequent word.

For bus speeds up to 66MHz Synchronous Burst Static RAM (Sync SRAM) offers even faster performance, being capable of 2-1-1-1 burst cycles. However, with bus speeds above 66MHz its performance drops to 3-2-2-2, significantly slower than PB SRAM.

There is also asynchronous cache, which is cheaper and slower because it isn’t timed to a clock cycle. With asynchronous SRAM, available in speeds between 12 and 20ns, all burst read cycles have a timing of 3-2-2-2 on a 50 to 66MHz CPU bus, which means that there are two wait-states for the lead-off cycle and one wait-state for the following three transfers of the burst cycle.

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