Pentium Pro (P6) 6th generation x86 History

The P6 microarchitecture is the sixth generation of Intel’s x86 processor architecture, first implemented in the design of the Pentium Pro CPU, introduced in 1995 as the successor to the original P5 Pentium design. The Pentium Pro introduced several unique architectural features that had never been seen in a PC processor before and was the first mainstream CPU to radically change how it executed instructions, by translating them into RISC-like micro-instructions and executing these on a highly advanced internal core. It also featured a dramatically higher-performance secondary cache compared to all earlier processors. Instead of using motherboard-based cache running at the speed of the memory bus, it used an integrated Level 2 cache with its own bus, running at full processor speed, typically three times the speed that the cache runs at on the Pentium. Some of the other techniques first used in the x86 space in the P6 core include: Superpipelining, the Pentium Pro having a 14-stage pipeline compared to the Pentium’s 5-stage Wider 36-bit physical address bus to support more than 4 GB of physical memory Speculative execution and out-of-order completion, requiring new retire units in the execution core which lessened pipeline stalls and contributed to the Pentium Pro\’s greater speed scaling Register renaming, which enabled more efficient execution of multiple instructions in the pipeline. Intel’s first new chip since the Pentium Pro took almost a year and a half to produce, and when it finally appeared the Pentium II proved to be very much an evolutionary step from the Pentium Pro. This fuelled the speculation that one of Intel’s primary goals in making the Pentium II...

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