The P6 microarchitecture is the sixth generation of Intel’s x86 processor architecture, first implemented in the design of the Pentium Pro CPU, introduced in 1995 as the successor to the original P5 Pentium design.
The Pentium Pro introduced several unique architectural features that had never been seen in a PC processor before and was the first mainstream CPU to radically change how it executed instructions, by translating them into RISC-like micro-instructions and executing these on a highly advanced internal core. It also featured a dramatically higher-performance secondary cache compared to all earlier processors. Instead of using motherboard-based cache running at the speed of the memory bus, it used an integrated Level 2 cache with its own bus, running at full processor speed, typically three times the speed that the cache runs at on the Pentium.
Some of the other techniques first used in the x86 space in the P6 core include:
- Superpipelining, the Pentium Pro having a 14-stage pipeline compared to the Pentium’s 5-stage
- Wider 36-bit physical address bus to support more than 4 GB of physical memory
- Speculative execution and out-of-order completion, requiring new retire units in the execution core which lessened pipeline stalls and contributed to the Pentium Pro\’s greater speed scaling
- Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
Intel’s first new chip since the Pentium Pro took almost a year and a half to produce, and when it finally appeared the Pentium II proved to be very much an evolutionary step from the Pentium Pro. This fuelled the speculation that one of Intel’s primary goals in making the Pentium II was to get away from the expensive integrated Level 2 cache that was so hard to manufacture on the Pentium Pro. Architecturally, the Pentium II is not very different from the Pentium Pro, with a similar x86 emulation core and most of the same features.
The Pentium II improved on the Pentium Pro architecturally by doubling the size of the Level 1 cache to 32KB, using special caches to improve the efficiency of 16-bit code processing (the Pentium Pro was optimised for 32-bit processing and did not deal with 16-bit code quite as well) and increasing the size of the write buffers. However, the most talked about aspect of the new Pentium II was its packaging. The integrated Pentium Pro secondary cache, running at full processor speed, was replaced on the Pentium II with a special small circuit board containing the processor and 512KB of secondary cache, running at half the processor\’s speed. This assembly, termed a single-edge cartridge (SEC), was designed to fit into a 242-pin slot (Socket 8) on the new style Pentium II motherboard.
Intel\’s Pentium III – launched in the Spring of 1999 – failed to introduced any architectural improvements beyond the addition of 70 new Streaming SIMD Extensions. This afforded rival AMD the opportunity to take the lead in the processor technology race, which it seized a few months later with the launch of its Athlon CPU – the first seventh-generation processor.
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, being characterised by low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).
- Principles of CPU architecture – logic gates, MOSFETS and voltage
- Basic structure of a Pentium microprocessor
- Microprocessor Evolution
- IA-32 (Intel Architecture 32 ) – base instruction set for 32 bit processors
- Pentium P5 microarchitecture – superscalar and 64 bit data
- Pentium Pro (P6) 6th generation x86 microarchitecture
- Dual Independent Bus (DIB) – frontside and backside data bus CPU architecture
- NetBurst – Pentium 4 7th generation x86 CPU microarchitecture
- Intel Core – 8th generation CPU architecture
- Moore’s Law in IT Architecture
- Architecture Manufacturing Process
- Copper Interconnect Architecture
- TeraHertz Technology
- Software Compatibility
- IA-64 Architecture
- Illustrated guide to high-k dielectrics and metal gate electrodes