Intel Core – 8th generation CPU architecture

It was at the Intel Development Forum in March 2006 that Intel released details of its new Intel Core microarchitecture, the successor to the NetBurst and mobile Pentium M architectures and foundation for the company’s forthcoming multi-core server, desktop and mobile processors. Building on the power-saving philosophy begun with the Mobile Intel Pentium M processor microarchitecture and existing Intel Pentium 4 processor technologies, the new microarchitecture features a number of important advances: Intel Wide Dynamic Execution: Delivers more instructions per clock cycle, improving execution and energy efficiency. Every execution core is wider, allowing each core to complete up to four full instructions simultaneously using an efficient 14-stage pipeline. Intel Intelligent Power Capability: Includes features that further reduce power consumption by intelligently powering on individual logic subsystems only when required. Intel Advanced Smart Cache: This includes a shared L2 cache to reduce power by minimising memory traffic and increase performance by allowing one core to utilise the entire cache when the other core is idle. Intel Smart Memory Access: Yet another feature that improves system performance by hiding memory latency and thus optimising the use of data bandwidth out to the memory subsystem. Intel Advanced Digital Media Boost: Now many 128-bit SSE, SSE2 and SSE3 instructions execute within only one cycle. This effectively doubles the execution speed for these instructions which are used widely in multimedia and graphics applications. Dynamic execution is a combination of techniques (dataflow analysis, speculative execution, out of order execution, and super scalar) that Intel first implemented in the P6 microarchitecture used in the Pentium Pro processor, Pentium II processor, and Pentium III processors. For its...

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