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Pentium P5 microarchitecture – superscalar and 64 bit data

First introduced in 1993, the Pentium was the successor to Intel’s 486 line of CPUs and the defining processor of the fifth generation.

The original Pentium microprocessor had the internal code name P5, and was a pipelined in-order superscalar microprocessor, produced using a 0.8 µm process. It was followed by the P54, a shrink of the P5 to a 0.6 µm process, which was dual-processor ready and had an internal clock speed different from the front side bus (it’s much more difficult to increase the bus speed than to increase the internal clock). In turn, the P54 was followed by the P54C, which used a 0.35µm process – a pure CMOS process, as opposed to the Bipolar CMOS process that was used for the earlier Pentiums.

The principal architectural changes that explained the Pentium’s greatly increased performance over the 486 chips that preceded it were its:

  • Superscalar architecture: The Pentium has two datapaths (pipelines) that allow it to complete more than one instruction per clock cycle. One pipe (called U) can handle any instruction, while the other (called V) can handle the simplest, most common instructions. The use of more than one pipeline is characteristic of RISC processor designs, and signalled the start of what was to become Intel’s increasing use of RISC techniques on its Pentium family of processors.
  • 64-bit data path: This doubling of the data bus width meant that twice the amount of information previous chips could manage was read with each memory fetch.

The subsequent P55C Pentium MMX processor was based on the P5 core and used the 0.35µm fabrication process. It offered further significant improvements by doubling the size of the on-board primary cache to 32KB and by an extension to the instruction set to optimise the handling of multimedia functions.

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