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Dual Independent Bus (DIB) – frontside and backside data bus CPU architecture

The Dual Independent Bus (DIB) architecture – first implemented in the Pentium Pro processor – was created to aid processor bus bandwidth. Having two (dual) independent buses enables the Pentium II processor to access data from either of its buses simultaneously and in parallel, rather than in a singular sequential manner as in a single bus system.

The processor reads and writes data to and from the Level 2 cache using a specialised high-speed bus. Called the backside bus, it’s separate from the CPU to main memory system bus (now called the frontside bus). The DIB architecture allows the processor to use both buses simultaneously, and also confers other advantages.

Dual

While the bus between the CPU and the Level 2 cache runs slower than on the conventional Pentium Pro (at half the processor clock speed), it’s extremely scaleable. As the processor gets faster, so does the cache, independent of the frontside bus. Additionally, frontside bus speeds can increase without affecting the Level 2 cache bus. It’s also believed that having the memory on the same silicon as the CPU badly affected the yields of the 512KB Pentium Pro, keeping prices high. The pipelined frontside bus also enables multiple simultaneous transactions (instead of singular sequential transactions), accelerating the flow of information within the system and boosting overall performance.

Together the Dual Independent Bus architecture improvements provide up to three times the bandwidth performance of a single bus architecture processor – as well as supporting the evolution to a 100MHz system bus.

  • Principles of CPU architecture – logic gates, MOSFETS and voltage
  • Basic structure of a Pentium microprocessor
  • Microprocessor Evolution
  • IA-32 (Intel Architecture 32 ) – base instruction set for 32 bit processors
  • Pentium P5 microarchitecture – superscalar and 64 bit data
  • Pentium Pro (P6) 6th generation x86 microarchitecture
  • Dual Independent Bus (DIB) – frontside and backside data bus CPU architecture
  • NetBurst – Pentium 4 7th generation x86 CPU microarchitecture
  • Intel Core – 8th generation CPU architecture
  • Moore’s Law in IT Architecture
  • Architecture Manufacturing Process
  • Copper Interconnect Architecture
  • TeraHertz Technology
  • Software Compatibility
  • IA-64 Architecture
  • Illustrated guide to high-k dielectrics and metal gate electrodes

Filed Under: CPU Architecture Tagged With: backside bus, dual independent bus architecture, frontside bus

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