Serial Ports

National Semiconductor has made the UART chips which have driven the PC’s serial port ever since the emergence of IBM’s first PC.

The original PC serial interface used the INS8250-B UART chip. This could receive and transmit data at speeds of up to 56 Kbit/s and, in the days of 4.77MHz bus speeds and serial printers, was perfectly adequate. When the IBM-AT came along a new UART was required because of the increase in bus speed and the fact that the bus was now 16 bits wide. This new UART was known as the INS 16450 and its CPU read and write cycles were over five times faster than its 8-bit predecessor.

In an AT ISA-bus machine, all serial data transfers are handled by the CPU and each byte must pass through the CPU registers to get to memory or disk. This means that access times must be fast enough to avoid read overrun errors and transmission latency at higher bit rates. In fact when the IBM PC-AT came out, the performance of the INS16450 was adequate because the speed at which data was routinely transmitted through the serial port was significantly less than is possible with modern modems.


To understand the limitations of the INS 16450, it is necessary to recognise how the serial port interrupts the CPU which has to finish its current task, or service a higher-priority interrupt, before servicing the UART. This delay is the bus latency time associated with servicing the UART interrupt request. If the CPU cannot service the UART before the next data byte is received (by the UART from the serial port), data will be lost, with consequent retransmissions and an inevitable impact on throughput.

This condition is known as overrun error. At low bit rates the AT system is fast enough to read each byte from the UART receiver before the next byte is received. The higher the bit rate at the serial port, the higher the strain on the system to transfer each byte from the UART before the next is received. Higher bit rates cause the CPU to spend increasing amounts of time servicing the UART, thus making the whole system run inefficiently.

To attack this problem, National Semiconductor developed the NS16550A UART. The 16550 overcomes the previous problems by including First In First Out (FIFO) buffers on the receiver and transmitter, which dramatically improve performance on modem transfer speeds of 9.6 Kbit/s or higher.

The size of the receiver FIFO ensures that as many as 16 bytes are ready to transfer when the CPU services the UART receiver interrupt. The receiver can request transfer at FIFO thresholds of one, four, eight, 16 bytes full. This allows software to modify the FIFO threshold according to its current task and ensures that the CPU doesn’t continually waste time switching context for only a couple of bytes of data received.

The transmitter FIFO ensures that as many as 16 bytes can be transferred when the CPU services the UART transmit interrupt. This reduces the time lost by the CPU in context switching. However, since a time lag in servicing an transmitter usually has no penalty, CPU latency is of no concern when transmitting, although ultimate throughput may suffer.