It had been Intel’s original intention to introduce the Tualatin processor core long before it actually did, as a logical progression of the Pentium III family that would – as a consequence of its finer process technology – allow higher clock frequencies. In the event, the company was forced to switch its focus to the (still 0.18-micron) Pentium 4, on the basis that it represented a better short term prospect in its ongoing clocking war with AMD than the Tualatin which, of course, would require a wholesale switch to a 0.13-micron fabrication process. As a consequence it was not until mid-2001 that the new core appeared.
The Tualatin is essentially a 0.13-micron die shrink of its Coppermine predecessor. It does offer one additional performance enhancing feature however – Data Prefetch Logic (DPL). DPL analyses data access patterns and uses available FSB bandwidth to prefetch data into the processor’s L2 cache. If the prediction is incorrect, there is no associated performance penalty. If it’s correct, time to fetch data from main memory is avoided.
Although Tualatin processors are nominally Socket 370 compliant, clocking, voltage and signal level differences effectively mean that they will not work in existing Pentium III motherboards.
Since the release of the Pentium Pro, all Intel P6 processors have used Gunning Transceiver Logic+ (GTL+) technology for their FSB. The GTL+ implementation actually changed slightly from the Pentium Pro to the Pentium II/III, the latter implementing what is known as the Assisted Gunning Transceiver Logic+ (AGTL+) bus. Both GTL+ and AGTL+ use 1.5V signalling. Tualatin sees a further change, this time to an AGTL signalling bus that uses 1.25V signalling and is capable of a peak theoretical maximum throughput of 1.06GBps. Furthermore, the new core supports use of a differential bus clocking scheme – in addition to single-ended clocking – as a means of reducing Electromagnetic Interference (EMI) associated with higher clock speeds.
Because it is manufactured on a smaller process, Tualatin requires much less power than did the Coppermine core. The VRM8.4 specification used by its predecessor only provided support for voltages in increments of 0.05V. Tualatins CPUs require voltage regulators that comply with VRM8.8 specifications, allowing adjustments in increments of 0.025V.
Finally, Tualatin introduces a novelty in the exterior of the of the CPU. Its new FC-PGA2 packaging contains an Integrated Heat Spreader (IHS) designed to perform two important functions. The first is to improve heat dissipation by providing a larger surface area onto which a heatsink can be attached. The second is to afford protection against mechanical damage to the fragile processor core, not least against the accidental damage that can occur during the fitting of a heatsink.
Three Socket 370 versions of Tualatin were originally defined: the Pentium III-A desktop unit, the Pentium III-S server unit and the Pentium III-M mobile unit. The server and mobile versions both boast an increased L2 cache of 512KB. Consistent with the apparent desire to avoid making the Tualatin too much of a threat to the flagship Pentium 4 processor in the mainstream desktop market, the former has the same 256KB L2 cache configuration as its Coppermine predecessor.
The table below shows the various incarnations of the Pentium III desktop processor to date:
| Date | Codename | Transistors | L2 Cache | Fabrication (µm) | Speed (MHz) |
|---|---|---|---|---|---|
| 1999 | Katmai | 9,500,000 | 512KB | 0.25 | 450/500/550 |
| 1999 | Coppermine | 28,100,000 | 256KB (on-die) | 0.18 | 533 to 733MHz |
| 2000 | Coppermine | 28,100,000 | 256KB (on-die) | 0.18 | 850MHz to 1GHz |
| 2001 | Tualatin | 44,000,000 | 256KB (on-die) | 0.13 | 1.2GHz to 1.4GHz |
Not only was the Tualatin the company’s first CPU to be produced using a 0.13-micron fabrication process, it also marked Intel’s transition to the use of copper interconnects instead of aluminium.
Since the release of the Pentium Pro, all Intel P6 processors have used Gunning Transceiver Logic+ (GTL+) technology for their FSB. The GTL+ implementation actually changed slightly from the Pentium Pro to the Pentium II/III, the latter implementing what is known as the Assisted Gunning Transceiver Logic+ (AGTL+) bus. Both GTL+ and AGTL+ use 1.5V signalling. Tualatin sees a further change, this time to an AGTL signalling bus that uses 1.25V signalling and is capable of a peak theoretical maximum throughput of 1.06GBps. Furthermore, the new core supports use of a differential bus clocking scheme – in addition to single-ended clocking – as a means of reducing Electromagnetic Interference (EMI) associated with higher clock speeds.
Because it is manufactured on a smaller process, Tualatin requires much less power than did the Coppermine core. The VRM8.4 specification used by its predecessor only provided support for voltages in increments of 0.05V. Tualatins CPUs require voltage regulators that comply with VRM8.8 specifications, allowing adjustments in increments of 0.025V.
Finally, Tualatin introduces a novelty in the exterior of the of the CPU. Its new FC-PGA2 packaging contains an Integrated Heat Spreader (IHS) designed to perform two important functions. The first is to improve heat dissipation by providing a larger surface area onto which a heatsink can be attached. The second is to afford protection against mechanical damage to the fragile processor core, not least against the accidental damage that can occur during the fitting of a heatsink.
Three Socket 370 versions of Tualatin were originally defined: the Pentium III-A desktop unit, the Pentium III-S server unit and the Pentium III-M mobile unit. The server and mobile versions both boast an increased L2 cache of 512KB. Consistent with the apparent desire to avoid making the Tualatin too much of a threat to the flagship Pentium 4 processor in the mainstream desktop market, the former has the same 256KB L2 cache configuration as its Coppermine predecessor.
The table below shows the various incarnations of the Pentium III desktop processor to date:
| Date | Codename | Transistors | L2 Cache | Fabrication (µm) | Speed (MHz) |
|---|---|---|---|---|---|
| 1999 | Katmai | 9,500,000 | 512KB | 0.25 | 450/500/550 |
| 1999 | Coppermine | 28,100,000 | 256KB (on-die) | 0.18 | 533 to 733MHz |
| 2000 | Coppermine | 28,100,000 | 256KB (on-die) | 0.18 | 850MHz to 1GHz |
| 2001 | Tualatin | 44,000,000 | 256KB (on-die) | 0.13 | 1.2GHz to 1.4GHz |
Not only was the Tualatin the company’s first CPU to be produced using a 0.13-micron fabrication process, it also marked Intel’s transition to the use of copper interconnects instead of aluminium.
- Pentium Architecture
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