i875P Chipset

Originally, Intel had planned to introduce a 800MHz FSB in the context of the Prescott, the upcoming 90nm Pentium 4 core. However, in the event this was brought forward to the spring of 2003. The rationale was to extend the Pentium 4’s performance curve within the confines of their current 0.13-micron process, without having to increase clock speeds to unsustainable levels. The transition from 533MHz to 800MHz FSB was aided and abetted by an associated new chipset platform, the 875P chipset, formerly codenamed Canterwood.

A 64-bit 800MHz FSB provides 6.4GBps of bandwidth between the Memory Controller Hub (or Northbridge) and the CPU. In a move that appears to further reduce the strategic importance of DRDRAM in Intel’s product planning, and that had been signalled by the earlier E7205 chipset, the memory subsystem the 875P uses to balance bandwidth between the Memory Controller Hub (MCH) and memory banks is dual channel DDR SDRAM, all of the DDR400, DDR333 and DD266 variants.

Currently, there are two different strategies being employed in dual-channel memory controllers, one in which where each memory bank has its own memory channel and an arbiter distributes the load between them and the other to actually create a wider memory channel, thereby doubling up on standard DDR’s 64-bit data paths. The i875P employs the latter technique, with each pair of installed DIMMs acting as a 128-bit memory module, able to transfer twice as much data as a single-channel solution, without the need for an arbiter.

As a consequence, dual channel operation is dependent on a number of conditions being met, Intel specifying that motherboards should default to single-channel mode in the event of any of these being violated:

  • DIMMs must be installed in pairs
  • Both DIMMs must use the same density memory chips
  • Both DIMMs must use the same DRAM bus width
  • Both DIMMs must be either single-sided or dual-sided.

The 875P chipset also introduces two significant platform innovations:

  • Intel Performance Acceleration Technology (PAT), and
  • Communications Streaming Architecture (CSA).

PAT optimises memory access between the processor and system memory for platforms configured with both the new 800Mhz FSB and Dual-Channel DDR400 memory. CSA is a new communications architecture that creates a dedicated link from the Memory Controller Hub (MCH) to the network interface, thereby offloading network traffic from the PCI bus. Used in conjunction with the new Intel PRO/1000 CT Desktop Connection gigabit Ethernet controller, it is claimed that CSA doubles the networking bandwidth possible with traditional PCI bus-based solutions.

Additionally, the 875P chipset includes a high-performance AGP 8x graphics interface, integrated Hi-Speed USB 2.0, optional ECC is supported for users that demand memory data reliability and integrity and dual independent DMA audio engines, enabling a user to make a PC phone call whilst at the same time playing digital music streams. The chipset is also Intel’s first to offer native Serial ATA (SATA), a special version designated by the -R suffix adding RAID – albeit only RAID 0 (data striping) – support.