In the second half of 1997 EIDE’s 16.6 MBps limit was doubled to 33 MBps by the new Ultra ATA (also referred to as ATA-33 or Ultra DMA mode 2 protocol). As well as increasing the data transfer rate, Ultra ATA also improved data integrity by using a data transfer error detection code called Cyclical Redundancy Check ( CRC).
The original ATA interface is based on transistor-transistor logic (TTL) bus interface technology, which is in turn based on the old industry standard architecture ( ISA) bus protocol. This protocol uses an asynchronous data transfer method. Both data and command signals are sent along a signal pulse called a strobe, but the data and command signals are not interconnected. Only one type of signal (data or command) can be sent at a time, meaning a data request must be completed before a command or other type of signal can be sent along the same strobe.
Starting with ATA-2 the more efficient synchronous method of data transfer is used. In synchronous mode, the drive controls the strobe and synchronises the data and command signals with the rising edge of each pulse. Synchronous data transfers interpret the rising edge of the strobe as a signal separator. Each pulse of the strobe can carry a data or command signal, allowing data and commands to be interspersed along the strobe. To get improved performance in this environment, it is logical to increase the strobe rate. A faster strobe means faster data transfer, but as the strobe rate increases, the system becomes increasingly sensitive to electro-magnetic interference (EMI, also known as signal interference or noise) which can cause data corruption and transfer errors. ATA-2 includes PIO mode 4 or DMA Mode 2 which, with the advent of the Intel Triton chipset in 1994, allowed support for a higher data transfer rate of 16.6 MBps.
ATA-3 added the Self-Monitoring Analysis and Reporting Technology ( SMART) feature, which resulted in more reliable hard drives.
ATA-4 includes Ultra ATA which, in an effort to avoid EMI, makes the most of existing strobe rates by using both the rising and falling edges of the strobe as signal separators. Thus twice as much data is transferred at the same strobe rate in the same time period. While ATA-2 and ATA-3 transfer data at burst rates up to 16.6 Mbytes per second, Ultra ATA provides burst transfer rates up to 33.3 MBps. The ATA-4 specification adds Ultra DMA mode 2 (33.3 MBps) to the previous PIO modes 0-4 and traditional DMA modes 0-2. The Cyclical Redundancy Check (CRC) implemented by Ultra DMA was new to ATA. The CRC value is calculated on a per-burst basis by both the host and the HDD controller, and is stored in their respective CRC registers. At the end of each burst, the host sends the contents of its CRC register to the HDD controller, which compares the host’s value against its own. If the HDD controller reports an error to the host, the host retries the command that produced the CRC error.
ATA-4 also provided for the integration of the AT Attachment Program Interface (ATAPI) standard. Up until this time ATAPI – which provides a common interface for CD-ROM drives, tape backup drives and other removable storage drives – had been a separate standard.
ATA-5 includes Ultra ATA/66 which doubles the Ultra ATA burst transfer rate by reducing setup times and increasing the strobe rate. The faster strobe rate increases EMI, which cannot be eliminated by the standard 40-pin cable used by ATA and Ultra ATA. To eliminate this increase in EMI, a new 40-pin, 80-conductor cable was developed. This cable adds 40 additional grounds lines between each of the original 40 ground and signal lines. The additional 40 lines help shield the signal from EMI. The new connector remains plug-compatible with existing 40-pin headers and Ultra ATA/66 hard drives are backward-compatible with Ultra ATA/33 and DMA, and with existing EIDE/IDE hard drives, CD-ROM drives and host systems. The ATA-5 specification introduces new Cyclic Redundancy Check (CRC) error detection code and adds Ultra DMA modes 3 (44.4 MBps) and 4 (66.6 MBps) to the previous PIO modes 0-4, DMA modes 0-2, and Ultra DMA mode 2.
ATA-6 – also referred to as Ultra DMA mode 5 – soon followed. This increased higher burst data transfer rates to a maximum 100 MBps by reducing its signal voltage – and associated timing requirements – from 5V to 3.3V.
The table below shows that several components have improved with the evolution of the ATA interface, realising progressive speed and functionality gains since the first ATA specification was introduced in 1981:
|Max Transfer Modes||PIO 1||PIO 4
|Max Transfer Rate||4 MBps||16 MBps||16 MBps||33 MBps||66 MBps||100 MBps|
|Max Connections||2||2||2||2 per cable||2 per cable||2 per cable|
Ultra ATA/100 had been expected to be the final generation of Parallel ATA interface before the industry completed its transition to Serial ATA. However, in the event, ATA/133 – also known as UltraDMA 133 – was announced in mid-2001, increasing throughput yet again, this time to 133 MBps.
- What Is The System Bus?
- ISA Bus – Industry Standard Architecture
- Local Bus Interfaces
- PCI Bus Interfaces
- What is AGP and AGP Pro?
- Internal Interfaces Summary
- PCI-X Interfaces
- PCI Express Interfaces
- IDE Interfaces
- EIDE Interfaces
- Hard Disks – What IS ATA and Ultra ATA?
- Serial ATA (SATA) interface guide
- SCSI Explained – With Pictures
- SCSI Interface Evolution
- Fibre Channel Interfaces
- Hard Disks – What is Serial Storage Architecture?
- I/O Interface Standards
- How It Works: The Idea and Technology Behind USB
- IEEE 1394 Interfaces
- USB 2.0 Intefaces
- FireWire 800 Interfaces