The Level 1 cache, or primary cache, is on the CPU and is used for temporary storage of instructions and data organised in blocks of 32 bytes. Primary cache is the fastest form of storage. Because it’s built in to the chip with a zero wait-state (delay) interface to the processor’s execution unit, it is limited in size.
Level 1 cache is implemented using Static RAM (SRAM) and until recently was traditionally 16KB in size. SRAM uses two transistors per bit and can hold data without external assistance, for as long as power is supplied to the circuit. The second transistor controls the output of the first: a circuit known as a flip-flop – so-called because it has two stable states which it can flip between. This is contrasted to dynamic RAM (DRAM), which must be refreshed many times per second in order to hold its data contents.
SRAM is manufactured in a way rather similar to how processors are: highly integrated transistor patterns photo-etched into silicon. Each SRAM bit is comprised of between four and six transistors, which is why SRAM takes up much more space compared to DRAM, which uses only one (plus a capacitor). This, plus the fact that SRAM is also several times the cost of DRAM, explains why it is not used more extensively in PC systems.
Intel’s P55 MMX processor, launched at the start of 1997, was noteworthy for the increase in size of its Level 1 cache to 32KB. The AMD K6 and Cyrix M2 chips launched later that year upped the ante further by providing Level 1 caches of 64KB. 64Kb has remained the standard L1 cache size, though various multiple-core processors may utilise it differently.
For all L1 cache designs the control logic of the primary cache keeps the most frequently used data and code in the cache and updates external memory only when the CPU hands over control to other bus masters, or during direct memory access by peripherals such as optical drives and sound cards.
Some chipsets, such as the Pentium based Triton FX (and later), support a write back cache rather than a write through cache. Write through happens when a processor writes data simultaneously into cache and into main memory (to assure coherency). Write back occurs when the processor writes to the cache and then proceeds to the next instruction. The cache holds the write-back data and writes it into main memory when that data line in cache is to be replaced. Write back offers about 10% higher performance than write-through, but cache that has this function is more costly. A third type of write mode, write through with buffer, gives similar performance to write back.
- What is Level 1 (L1) Cache Memory?
- What is L2 (Level 2) cache memory?
- RAM or Main Memory – PC / computer memory (DIMM, DRAM, SDRAM)
- DRAM – Dynamic Random Access Memory
- FPM DRAM
- EDO (Extended Data Out) and BEDO (Burst Extended Data Out) DRAM
- SDRAM
- PC133 SDRAM
- DDR SDRAM explained
- DDR2 DRAM
- Dual Channel DDR Memory
- 1T SRAM
- Direct DRAM
- SIMMs
- DIMM Memory
- RIMMs Memory
- Memory Presence Detection
- Parity Memory
- ECC Memory
- Memory Upgrades
- The Evolution of Memory
- Flash Memory
- Magnetic RAM