Memory modules have traditionally been available in two basic flavours: non-parity and parity. Parity checking uses a ninth memory chip to hold checksum data on the contents of the other eight chips in that memory bank. If the predicted value of the checksum matches the actual value, then all is well. If it does not, then the contents of memory is corrupted and unreliable. In this event a non-maskable interrupt (NMI) is generated to instruct the system to shut down and thereby avoid any potential data corruption.
Parity checking is quite limited – only odd numbers of bit errors are detected (two parity errors in the same byte will cancel themselves out) and there’s no way of identifying the offending bits or fixing them – and in recent years the more sophisticated and more costly Error Check Code (ECC) memory has gained in popularity.
- What is Level 1 (L1) Cache Memory?
- What is L2 (Level 2) cache memory?
- RAM or Main Memory – PC / computer memory (DIMM, DRAM, SDRAM)
- DRAM – Dynamic Random Access Memory
- FPM DRAM
- EDO (Extended Data Out) and BEDO (Burst Extended Data Out) DRAM
- SDRAM
- PC133 SDRAM
- DDR SDRAM explained
- DDR2 DRAM
- Dual Channel DDR Memory
- 1T SRAM
- Direct DRAM
- SIMMs
- DIMM Memory
- RIMMs Memory
- Memory Presence Detection
- Parity Memory
- ECC Memory
- Memory Upgrades
- The Evolution of Memory
- Flash Memory
- Magnetic RAM