All types of memory are addressed as an array of rows and columns, and individual bits are stored in each cell of the array. With standard DRAM or FPM DRAM, which comes with access times of 70ns or 60ns, the memory management unit reads data by first activating the appropriate row of the array, activating the correct column, validating the data and transferring the data back to the system. The column is then deactivated, which introduces an unwanted wait state where the processor has to wait for the memory to finish the transfer. The output data buffer is then turned off, ready for the next memory access.

At best, with this scheme FPM can achieve a burst rate timing as fast as 5-3-3-3. This means that reading the first element of data takes five clock cycles, containing four wait-states, with the next three elements each taking three.

DRAM speed improvements have historically come from process and photolithography advances. More recent improvements in performance however have resulted from changes to the base DRAM architecture that require little or no increase in die size. Extended Data Out (EDO) memory is an example of this.

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