Unlike parity memory, which uses a single bit to provide protection to eight bits, ECC uses larger groupings. Five ECC bits are needed to protect each eight-bit word, six for 16-bit words, seven for 32-bit words and eight for 64-bit words.
Additional code is needed for ECC protection, and the firmware that generates and checks the ECC can be in the motherboard itself or built into the motherboard chipsets (most Intel chips now include ECC code). The downside is that ECC memory is relatively slow – it requires more overhead than parity memory for storing data and causes around a 3% performance loss in the memory sub-system. Generally, use of ECC memory is limited to so-called mission-critical applications and is therefore more commonly found on servers than on desktop systems.
What the firmware does when it detects an error can differ considerably. Modern systems will automatically correct single-bit errors, which account for most RAM errors, without halting the system. Many can also fix multi-bit errors on the fly or, where that’s not possible, automatically reboot with the bad memory mapped out.
- What is Level 1 (L1) Cache Memory?
- What is L2 (Level 2) cache memory?
- RAM or Main Memory – PC / computer memory (DIMM, DRAM, SDRAM)
- DRAM – Dynamic Random Access Memory
- FPM DRAM
- EDO (Extended Data Out) and BEDO (Burst Extended Data Out) DRAM
- PC133 SDRAM
- DDR SDRAM explained
- DDR2 DRAM
- Dual Channel DDR Memory
- 1T SRAM
- Direct DRAM
- DIMM Memory
- RIMMs Memory
- Memory Presence Detection
- Parity Memory
- ECC Memory
- Memory Upgrades
- The Evolution of Memory
- Flash Memory
- Magnetic RAM