Historically, while much more cost effective than SRAM per Megabit, traditional DRAM has always suffered speed and latency penalties making it unsuitable for some applications. Consequently, product manufacturers have often been forced to opt for the more expensive, but faster SRAM technology. By 2000, however, system designers had another option available to them, and one that offers the best of both worlds: fast speed, low cost, high density and lower power consumption.
Though the inventor of 1T-SRAM – Monolithic System Technology Inc. (MoSys) – calls its design an SRAM, it is in fact based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the 1T-SRAM unique is that it offers a true SRAM-style interface that hides all refresh operations from the memory controller.
Traditionally, SRAMs have been built using a bulky four or six transistor (4T, 6T) cell. The MoSys 1T-SRAM device is built on a single transistor (1T) DRAM cell, allowing a reduction in die size by between 50% and 80% compared to SRAMs of similar density. Moreover, its high density is achieved whilst at the same time maintaining the refresh-free interface and low latency random memory access cycle time associated with traditional six-transistor SRAM cells. As if these exceptional density and performance characters weren’t enough, 1T-SRAM technology also offers dramatic power consumption savings by using under a quarter of the power of traditional SRAM memories!
1T-SRAM is an innovation that promises to dramatically change the balance between the two traditional memory technologies. At the very least it will provide DRAM makers with the opportunity to squeeze significantly more margin from their established DRAM processes.
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