pctechguide.com

DRAM – Dynamic Random Access Memory

DRAM chips are large, rectangular arrays of memory cells with support logic that is used for reading and writing data in the arrays, and refresh circuitry to maintain the integrity of stored data. Memory arrays are arranged in rows and columns of memory cells called wordlines and bitlines, respectively. Each memory cell has a unique location or address defined by the intersection of a row and a column.

DRAM is manufactured using a similar process to how processors are: a silicon substrate is etched with the patterns that make the transistors and capacitors (and support structures) that comprise each bit. It costs much less than a processor because it is a series of simple, repeated structures, so there isn’t the complexity of making a single chip with several million individually-located transistors and DRAM is cheaper than SRAM and uses half as many transistors. Over the years, several different structures have been used to create the memory cells on a chip, and in today’s technologies the support circuitry generally includes:

  • sense amplifiers to amplify the signal or charge detected on a memory cell
  • address logic to select rows and columns
  • Row Address Select (RAS) and Column Address Select (CAS) logic to latch and resolve the row and column addresses and to initiate and terminate read and write operations
  • read and write circuitry to store information in the memory’s cells or read that which is stored there
  • internal counters or registers to keep track of the refresh sequence, or to initiate refresh cycles as needed
  • Output Enable logic to prevent data from appearing at the outputs unless specifically desired.

A transistor is effectively a switch which can control the flow of current – either on, or off. In DRAM, each transistor holds a single bit: if the transistor is open, and the current can flow, that’s a 1; if it’s closed, it’s a 0. A capacitor is used to hold the charge, but it soon escapes, losing the data. To overcome this problem, other circuitry refreshes the memory, reading the value before it disappears completely, and writing back a pristine version. This refreshing action is why the memory is called dynamic. The refresh speed is expressed in nanoseconds (ns) and it is this figure that represents the speed of the RAM. Most Pentium-based PCs use 60 or 70ns RAM.

The process of refreshing actually interrupts/slows down the accessing of the data but clever cache design minimises this. However, as processor speeds passed the 200MHz mark, no amount of cacheing could compensate for the inherent slowness of DRAM and other, faster memory technologies have largely superseded it.

DRAM Timing and Signals

The most difficult aspect of working with DRAM devices is resolving the timing requirements. DRAMs are generally asynchronous, responding to input signals whenever they occur. As long as the signals are applied in the proper sequence, with signal durations and delays between signals that meet the specified limits, the DRAM will work properly. These are few in number, comprising:

  • Row Address Select: The /RAS circuitry is used to latch the row address and to initiate the memory cycle. It is required at the beginning of every operation. /RAS is active low; that is, to enable /RAS, a transition from a high voltage to a low voltage level is required. The voltage must remain low until /RAS is no longer needed. During a complete memory cycle, there is a minimum amount of time that /RAS must be active, and a minimum amount of time that /RAS must be inactive, called the /RAS precharge time. /RAS may also be used to trigger a refresh cycle (/RAS Only Refresh, or ROR).
  • Column Address Select: /CAS is used to latch the column address and to initiate the read or write operation. /CAS may also be used to trigger a /CAS before /RAS refresh cycle. This refresh cycle requires /CAS to be active prior to /RAS and to remain active for a specified time. It is active low. The memory specification lists the minimum amount of time /CAS must remain active to initiate a read or write operation. For most memory operations, there is also a minimum amount of time that /CAS must be inactive, called the /CAS precharge time. (An ROR cycle does not require /CAS to be active.)
  • Address: The addresses are used to select a memory location on the chip. The address pins on a memory device are used for both row and column address selection (multiplexing). The number of addresses depends on the memory’s size and organisation. The voltage level present at each address at the time that /RAS or /CAS goes active determines the row or column address, respectively, that is selected. To ensure that the row or column address selected is the one that was intended, set up and hold times with respect to the /RAS and /CAS transitions to a low level are specified in the DRAM timing specification.
  • Write Enable: The /WE signal is used to choose a read operation or a write operation. A low voltage level signifies that a write operation is desired; a high voltage level is used to choose a read operation. The operation to be performed is usually determined by the voltage level on /WE when /CAS goes low (Delayed Write is an exception). To ensure that the correct operation is selected, set up and hold times with respect to /CAS are specified in the DRAM timing specification.
  • Output Enable: During a read operation, this control signal is used to prevent data from appearing at the output until needed. When /OE is low, data appears at the data outputs as soon as it is available. /OE is ignored during a write operation. In many applications, the /OE pin is grounded and is not used to control the DRAM timing.
  • Data In or Out: The DQ pins (also called Input/Output pins or I/Os) on the memory device are used for input and output. During a write operation, a voltage (high=1, low=0) is applied to the DQ. This voltage is translated into the appropriate signal and stored in the selected memory cell. During a read operation, data read from the selected memory cell appears at the DQ once access is complete and the output is enabled (/OE low). At most other times, the DQs are in a high impedance state; they do not source or sink any current, and do not present a signal to the system. This also prevents DQ contention when two or more devices share the data bus.

Comments

Guides

Recent Posts

Core i3 2nd Gen

In 2011 the 2nd generation of the Core i3 processors was introduced. These processors were based on the Sandy Bridge architecture. This came as a … [Read More...]