By the summer of 1999 the proponents of Future I/O and NGIO had called a truce and agreed to merge the two technologies into a new specification. Originally, this went by the working name of System I/O. However, by the end of the year it had been renamed InfiniBand. In the end the technology – which would have required the industry to adopt new hardware and software – proved just a little too revolutionary for most computing companies to feel comfortable about adopting and by the end of 2001 it had pretty much been relegated to a niche market.
In the summer of 2001 Intel had signalled that the writing was on the wall for Infiniband when it developed yet another technology, which it called Third-Generation Input/Output (3GIO). Also known as Arapahoe, this was adopted by the PCI SIG in the summer of 2001. Early the following year, ownership of 3GIO was transferred to the PCI-SIG where it was re-named the PCI Express Architecture. Finally the industry had reached a decision on PCI’s successor. It is one which represents a more evolutionary approach than some of the schemes that had been proposed earlier, the move to PCI Express being expected to be similar to the ISA/EISA to PCI transition experienced in the early 1990s.
The PCI Express Architecture defines a flexible, scalable, high-speed, serial, point-to-point, hot pluggable/hot swappable interconnect that is software-compatible with PCI. Unlike its predecessor, PCI Express is a serial point-to-point interconnect system, similar to AMD’s
A PCX interface comprises two pairs of wires, referred to as a lane, and a single PCX lane is known as a 1x interface. Lanes may be aggregated, and a maximum possible 32 data lanes provides total bandwidth of 16 GBps, sufficient to support the control plane and data plane demands of communications systems well into the foreseeable future. Moreover, it is an architecture that allows real-time data – such as streamed video or audio – to be tagged so that an I/O system can prioritise its flow throughout the platform.
Whilst PCI Express is positioned as a complementary technology to PCI and PCI-X, it’s intended to replace
The first chipsets to provide support for PCI Express – codenamed Alderwood and Grantsdale – were announced in summer of 2004, with complete PCs emerging shortly after.