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Intel’s Triton Chipsets Explained – their history, architecture and development

Triton430FX

Introduced in early 1995, the 82430FX – to give it its full name – was Intel’s first Triton chipset and conformed to the PCI 2.0 specification. It introduced support for EDO memory configurations of up to 128MB and for pipelined burst cache and synchronous cache technologies. However, it did not support a number of emerging technologies such as SDRAM and USB and was superseded in 1996 – little more than a year after its launch – by a pair of higher performance chipsets.

Triton430VX

The Triton 430VX chipset conforms to the PCI 2.1 specification, and is designed to support Intel’s Universal Serial Bus (USB) and Concurrent PCI standards. With the earlier 430FX, a bus master (on the ISA or PCI bus), such as a network card or disk controller, would lock the PCI bus whenever it transferred data in order to have a clear path to memory. This interrupted other processes, and was inefficient because the bus master would never make full use of the 100 MBps bandwidth of the PCI bus. With Concurrent PCI, the chipset can wrest control of the PCI bus from an idle bus master to give other processes access on a timeshare basis. Theoretically, this should allow for data transfer rates of up to 100 MBps, 15% more than the 430FX chipset, and smooth intensive PCI tasks such as video playback when bus masters are present.

The 430VX chipset was aimed fairly and squarely at the consumer market. It was intended to speed up multimedia and office applications, and it was optimised for 16-bit. Furthermore, it was designed to work with SDRAM, a special type of memory that’s optimised for intensive multimedia processing. Although the performance gains are slight for this type of RAM over EDO RAM, the advantage is that it can operate efficiently from a single Dual In-line Memory Module (DIMM) and does not need to be paired.

The 430VX provided improved EDO memory timings which was supposed to allow cacheless systems to be built without compromising performance, at least compared to a PC with asynchronous cache. In practice, though, most manufacturers continued to provide at least some secondary cache, with most using synchronous cache to maximise performance.

Triton430HX

The Triton 430HX chipset is geared towards business machines and was developed with networking, video conferencing and MPEG video playback in mind. It supports multiple processors, has been optimised for 32-bit operation and to work with large memory arrays (up to 512MB) and provides error control (ECC) facilities on the fly when 32-bit parity SIMMs are used. The 430HX does not support SDRAM.

The biggest difference between the HX and VX chipsets is the packaging. Where the VX consists of four separate chips, all built using the traditional plastic quad flat packaging, the HX chipset comprises just two chips, the 82439HX System Controller (SC), which manages the host and PCI buses, and the 82371SB PIIX3 for the ISA bus and all the ports.

The SC comes in a new ball grid array (BGA) packaging which reduces overall chip size and makes it easier to incorporate onto motherboard designs. It exerts the greatest influence on the machine’s CPU performance, as it manages communications between the CPU and memory. The CPU has to be fed data from the secondary cache as quickly as possible, and if the necessary data isnt already in the cache, the SC fetches it from main memory and loads it into the cache. The SC also ensures that data written into cache by the CPU is flushed back into main memory.

The PIIX3 chip manages the many processes involved in getting data into and out of RAM from the other devices in the PC. It provides two EIDE channels, both of which can accept two drives. IDE drives contain most of the controlling circuitry built into the hard disk itself, so the PIIX is mainly responsible for shifting data from the drives into RAM and back as quickly as possible. It also provides two 115,200bit/s buffered serial ports, an error correcting Enhanced Parallel Port, a PS/2 mouse port and a keyboard controller. The PIIX also supports additional connections that many motherboards have yet to adopt as the norm, such as a Universal Serial Bus connector and an infrared port.

Triton430TX

The Triton 430TX includes all the features found on the earlier chipsets, including Concurrent PCI, USB support, aggressive EDO RAM timings and SDRAM support and is optimised for MMX processors and is designed to be used in both desktop and mobile computers.

The Triton 430TX also continues the high-integration two-chip BGA packaging first seen with the 430HX chipset, comprising the 82439TX System Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator (PIIX4). The former integrates the cache and main memory DRAM control functions and provides bus control to transfers between the CPU, cache, main memory, and the PCI Bus. The latter is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function.

The diagram below provides an overview of the overall architecture and shows the division of functionality between the System Controller and the Peripheral Bus Controller components – which are often referred to as Northbridge and Southbridge chipsets respectively.

Triton

Dynamic Power Management Architecture – DPMA

The TX incorporates the Dynamic Power Management Architecture (DPMA) which reduces overall system power consumption and offers intelligent power-saving features like suspend to RAM and suspend to disk. The TX chipset also supports the new Ultra DMA disk protocol which enables a data throughput of 33 MBps from the hard disk drive to enhance performance in the most demanding applications.

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