Pentium Xeon

In June 1998 Intel introduced its Pentium II Xeon processor, rated at 400MHz. Technically, Xeon represented a combination of Pentium Pro and Pentium II technology and was designed to offer outstanding performance in critical applications for workstations and servers. Using the new Slot 2 interface, Xeon was nearly twice the size of Pentium II, primarily because of the increased Level 2 cache. The cache system was similar to the type used in the Pentium Pro, which was one of the Xeons main cost factors. Another was the fact that ECC SRAM was to be standard in all Xeons.

When launched, the chip was available with either 512KB or 1MB of Level 2 cache. The former was intended for the workstation market, the latter was intended for server implementations. A 2 MB version appeared later in 1999.

Like the 350MHz and 400MHz Pentium II CPUs, the Front Side Bus ran at 100MHz for improved system bandwidth. The most dramatic improvement over the standard Pentium II was that the Level 2 cache ran at the same speed as the core of the CPU, unlike Slot 1 designs which limited the Level 2 cache to half the core frequency, allowing Intel to use cheaper off-the-shelf burst SRAM as Level 2 cache, rather than fabricating its own custom SRAM. The far more expensive custom-fabbed full-speed Level 2 cache was the primary reason for the price differential between the Slot 1 and Slot 2 parts.

Another limitation that Slot 2 overcame was the dual-SMP (symmetric multiprocessor) limit. The inability to run multiprocessor Pentium II systems with more than two CPUs had been the main reason for the Pentium Pro’s survival in the high-end server sector, where multiple processor configurations were often required. Systems based on the Pentium II Xeon processor could be configured to scale to four or eight processors and beyond.

Although Intel had decided to target the Xeon at both the workstation and server markets, it developed different motherboard chipsets for each of these. The 440GX chipset was built around the core architecture of the 440BC chipset and was intended for workstations. The 450NX, on the other hand, was designed specifically for the server market.

By early 1999 the take-up of the Xeon processor had been rather slow. This was largely due to the fact that Xeon processors weren’t available in sufficiently higher clock speeds than the fastest Pentium II to justify their high price premium. However, an innovative product from SuperMicro held out the prospect of improving the Xeon’s fortunes. Using the fact that both the Pentium II and Xeon CPUs shared the same P6 microarchitecture and therefore operated in very similar ways, SuperMicro designed a simple-looking adapter that allowed a standard Pentium II/350 or faster to slot into their new S2DGU motherboard. This ingenious design made it possible – for the first time – to upgrade between two different x86 architectures without having to change motherboards.

Close on the heels of the launch of the Pentium III in the spring of 1999 came the Pentium III Xeon, formerly codenamed Tanner. This was basically a Pentium Xeon with the new Streaming SIMD Extensions (SSE) instruction set added. Targeted at the server and workstation markets, the Pentium III Xeon was initially shipped as a 500MHz processor with either 512KB, 1MB or 2MB of Level 2 cache. In the autumn of 1999 the Xeon moved to the 0.18-micron Cascade’s core, with speeds increasing from an initial 667MHz to 1GHz by late 2000.

In the spring of 2001 the first Pentium 4 based Xeon was released, at clock speeds of 1.4, 1.5 and 1.7Ghz. Based on the Foster core, this was identical to a standard Pentium 4 apart from its microPGA Socket 603 form factor and its dual processor capability. The Pentium 4 Xeon was supported by the i860 chipset, very similar to the desktop i850 chipset with the addition of dual processor support, 2×64-bit PCI buses and Memory Repeater Hubs (MRH-R) to increase the maximum memory size to 4GB (8 RIMMs). The i860 also featured a prefetch cache to reduce memory latency and help improve bus contention for dual processor systems. A year later a multiprocessor version was released, allowing 4 and 8-way Symmetric Multiprocessing (SMP) and featuring an integrated Level 3 cache of 512Kb or 1Mb.