EDO and BEDO DRAM – History and Evolution of Product

Extended Data Out DRAM comes in 70ns, 60ns and 50ns speeds. 60ns is the slowest that should be used in a 66MHz bus speed system (i.e. Pentium 100MHz and above) and the Triton HX and VX chipsets can also take advantage of the 50ns version. EDO DRAM doesn’t demand that the column be deactivated and the output buffer turned off before the next data transfer starts. It therefore achieves a typical burst timing of 5-2-2-2 at a bus speed of 66MHz and can complete some memory reads a theoretical 27% faster than FPM DRAM.


Burst EDO DRAM is an evolutionary improvement in EDO DRAM that contains a pipeline stage and a 2-bit burst counter. With the conventional DRAMs such as FPM and EDO, the initiator accesses DRAM through a memory controller. The controller must wait for the data to become ready before sending it to the initiator. BEDO eliminates the wait-states thus improving system performance by up to 100% over FPM DRAM and up to 50% over standard EDO DRAM, achieving system timings of 5-1-1-1 when used with a supporting chipset.

Despite the fact that BEDO arguably provides more improvement over EDO than EDO does over FPM the standard has lacked chipset support and has consequently never really caught on, losing out to Synchronous DRAM (SDRAM).