Definition of cache
There's 13 results for your query.
Asynchronous Cache
Definition: An SRAM that does not require a clock signal to validate its control signals. About 30% lower in price and performance compared to synchronous cache.
Category: Memory
Guides: Asynchronous Cache
Cache
Definition: An intermediate storage capacity between the processor and the RAM or disk drive. The most commonly used instructions are held here, allowing for faster processing.
Category: Motherboard
Cache Buffer
Definition: An intermediate storage capacity between the processor and the disk drive used to store data likely to be requested next. Also known as Data Buffer. See also Look Ahead.
Category: Disk Storage
Cache Controller
Definition: The circuit in control of the interface between the CPU, cache and DRAM (main memory).
Category: Memory
Cache Hit
Definition: When the address requested by the CPU is found in cache. Conversely, cache miss is when its not found.
Category: Memory
Cache Memory
Definition: A small block of high-speed memory (usually SRAM) located between the CPU and main memory that is used to store frequently requested data and instructions. Properly designed, a cache improves system performance by reducing the need to access the system's slower main memory for every transaction.
Category: Memory
Data Cache
Definition: The Data Cache works very closely with the "processing partners", the ALU, Registers and the Decode Unit. This is where specially labelled data from the Decode Unit are stored for later use by the ALU and where final results are prepared for distribution to different parts of the computer.
Category: Microprocessors
Guides: Data Cache
Instruction Cache
Definition: The Instruction Cache is a warehouse of instructions right on the chip, so that the microprocessor doesn't have to stop and look in the computer's main memory for instructions. This quick access makes processing fast as instructions are "fetched" to the Prefetch Unit where they are put in the proper order for processing.
Category: Microprocessors
Guides: Instruction Cache
Level 1 Cache - L1 Cache
Definition: Cache that is closest to the processor, typically located inside the CPU chip. Can be implemented either as a unified cache or as separate sections for instructions and data. Also referred to as primary cache or internal cache.
Category: Memory
Guides: Level 1 Cache - L1 Cache
Level 2 Cache - L2 Cache
Definition: Cache that is second closest to the processor, typically located on the system board. Also referred to as secondary cache and external cache.
Category: Memory
Guides: Level 2 Cache - L2 Cache
Level 3 Cache - L3 Cache
Definition: A memory reservoir near the processor that boosts performance beyond that possible with traditional two-level cache designs. First seen in early 1999 on AMD's K6-III CPU, a similar system was later used by Intel's 64-bit Itanium processor.
Category: Memory
Pipeline Burst Cache
Definition: A type of synchronous cache that uses two techniques to minimise processor wait states - a burst mode that pre-fetches memory contents before they are requested, and pipelining so that one memory value can be accessed in the cache at the same time that another memory value is accessed in DRAM.
Category: Memory
Synchronous Cache
Definition: An SRAM that requires a clock signal to validate its control signals. This enables the cache memory to run lockstep with the CPU. Can be either Burst or Pipelined Burst.
Category: Memory
Guides: Synchronous Cache